1. Assume a machine using Five-stage pipelining (IF – ID – MU- EX - WR) runs a program. Instruction-3 is a conditional branch instruction. If the condition is TRUE, CPU skips next three instructions. Instruction-8 is also a conditional branch instruction and if it is FALSE, program control returns to Instruction-4. Show at least 15-time steps of pipelining stages assuming that both Instructions 3 and 8 are evaluated TRUE. 1 2 IF ID MU 7 8 9 | 12 | 13 | 14 15 16 17 18 19 3 4 5 6 10 11 20 Instructions Inst-1 Inst-2 Inst-3 EX WR IF ID IF MU EX WR ID MU EX WR Inst-4 IF ID MU Inst-5 IF ID CLEAR Inst-6 IF Inst-7 IF ID MU EX WR Inst-8 IF ID MU EX WR Inst-9 IF ID MU EX WR Inst-10 IF ID MU EX WR Inst-11 IF ID MU EX WR Inst-12 IF ID MU EX WR Inst-13 IF ID MU EX

1. Assume a machine using Five-stage pipelining (IF – ID – MU- EX - WR) runs a program. Instruction-3 is a conditional branch instruction. If the condition is TRUE, CPU skips next three instructions. Instruction-8 is also a conditional branch instruction and if it is FALSE, program control returns to Instruction-4. Show at least 15-time steps of pipelining stages assuming that both Instructions 3 and 8 are evaluated TRUE. 1 2 IF ID MU 7 8 9 | 12 | 13 | 14 15 16 17 18 19 3 4 5 6 10 11 20 Instructions Inst-1 Inst-2 Inst-3 EX WR IF ID IF MU EX WR ID MU EX WR Inst-4 IF ID MU Inst-5 IF ID CLEAR Inst-6 IF Inst-7 IF ID MU EX WR Inst-8 IF ID MU EX WR Inst-9 IF ID MU EX WR Inst-10 IF ID MU EX WR Inst-11 IF ID MU EX WR Inst-12 IF ID MU EX WR Inst-13 IF ID MU EX

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 15VE: A(n) ________________ instruction always alters the instruction execution sequence. A(n)...

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