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Given the MIPS instruction sequence shown below. Assume this code is executed on a fi D, EXE, MEM, WB) pipelined MIPS CPU with the capability to finish the register write nalf cycle and the register reads in the second half cycle. 1. sll $t1, $s1, 2 2. add $t1, $s2, $ti 3. 1w $s3, 100 ($t1) 4. addi $s3, $s3, 1 5. slt $t2, $s3, $o

Given the MIPS instruction sequence shown below. Assume this code is executed on a fi D, EXE, MEM, WB) pipelined MIPS CPU with the capability to finish the register write nalf cycle and the register reads in the second half cycle. 1. sll $t1, $s1, 2 2. add $t1, $s2, $ti 3. 1w $s3, 100 ($t1) 4. addi $s3, $s3, 1 5. slt $t2, $s3, $o

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Given the MIPS instruction sequence shown below. Assume this code is executed on a five-stage (IF, ID, EXE, MEM, WB) pipelined MIPS CPU with the capability to finish the register write in the first half cycle and the register reads in the second half cycle. 1. sll $t1, $s1, 2 2. add $t1, $s2, $t1 3. lw $s3, 100 ($t1) 4. addi $3, $s3, 1 5. slt $t2, $s3, $0 a. Identify all the data dependences in the code if this pipelined CPU does not have any forwarding capability. b. If this pipelined CPU has forwarding capability, which dependences are data hazards that cannot be solved by forwarding?
Transcribed Image Text:Given the MIPS instruction sequence shown below. Assume this code is executed on a five-stage (IF, ID, EXE, MEM, WB) pipelined MIPS CPU with the capability to finish the register write in the first half cycle and the register reads in the second half cycle. 1. sll $t1, $s1, 2 2. add $t1, $s2, $t1 3. lw $s3, 100 ($t1) 4. addi $3, $s3, 1 5. slt $t2, $s3, $0 a. Identify all the data dependences in the code if this pipelined CPU does not have any forwarding capability. b. If this pipelined CPU has forwarding capability, which dependences are data hazards that cannot be solved by forwarding?
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