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Q3 Assume the following latencies for a single-issue processor. Instruction Producing Result FP MUL/DIV FP ADD/SUB Load Double Load Double Int ADD Latency in Clock Cycles 5 Instruction Using Result Another FP ALU op Another FP ALU op or Store Double FP ALU op Store Double Branch 4 2 1 Unroll and schedule the following code a minimum number of times until there are zero stalls. Write down the following and give their respective Clock Cycles/iteration. Unscheduled and not unrolled b. Scheduled and not unrolled c. Scheduled and minimally unrolled code to have zero stalls Clearly mention how many times you unrolled the loop to obtain zero stalls. Loop: L.D FO, O(R2) SUB.D F1, FO, F4 F5, F1, F6 ADD.D F3, FO, F2 I/ F4 contains a scalar constant // F6 contains a scalar constant // F2 contains a scalar constant DIV.D F3, O(R2) DADDI R2, R2, 8 S.D DADDI R4, DADDI R1, R1, -8 R6 BNEZ R1, Loop

Q3 Assume the following latencies for a single-issue processor. Instruction Producing Result FP MUL/DIV FP ADD/SUB Load Double Load Double Int ADD Latency in Clock Cycles 5 Instruction Using Result Another FP ALU op Another FP ALU op or Store Double FP ALU op Store Double Branch 4 2 1 Unroll and schedule the following code a minimum number of times until there are zero stalls. Write down the following and give their respective Clock Cycles/iteration. Unscheduled and not unrolled b. Scheduled and not unrolled c. Scheduled and minimally unrolled code to have zero stalls Clearly mention how many times you unrolled the loop to obtain zero stalls. Loop: L.D FO, O(R2) SUB.D F1, FO, F4 F5, F1, F6 ADD.D F3, FO, F2 I/ F4 contains a scalar constant // F6 contains a scalar constant // F2 contains a scalar constant DIV.D F3, O(R2) DADDI R2, R2, 8 S.D DADDI R4, DADDI R1, R1, -8 R6 BNEZ R1, Loop

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Q3 Assume the following latencies for a single-issue processor. Instruction Using Result Another FP ALU op Another FP ALU op or Store Double FP ALU op Store Double Branch Instruction Producing Result FP MUL/DIV FP ADD/SUB Latency in Clock Cycles 5 4 Load Double 2 Load Double Int ADD Unroll and schedule the following code a minimum number of times until there are zero stalls. Write down the following and give their respective Clock Cycles/iteration. a. Unscheduled and not unrolled b. Scheduled and not unrolled c. Scheduled and minimally unrolled code to have zero stalls Clearly mention how many times you unrolled the loop to obtain zero stalls. FO, O(R2) SUB.D F1, FO, F4 DIV.D F5, F1, F6 ADD.D F3, FO, F2 Loop: L.D // F4 contains a scalar constant // F6 contains a scalar constant // F2 contains a scalar constant F3, 0(R2) DADDI R2, R2, 8 S.D DADDI R4, RS, R6 DADDI R1, R1, -8 BNEZ R1, Loop
Transcribed Image Text:Q3 Assume the following latencies for a single-issue processor. Instruction Using Result Another FP ALU op Another FP ALU op or Store Double FP ALU op Store Double Branch Instruction Producing Result FP MUL/DIV FP ADD/SUB Latency in Clock Cycles 5 4 Load Double 2 Load Double Int ADD Unroll and schedule the following code a minimum number of times until there are zero stalls. Write down the following and give their respective Clock Cycles/iteration. a. Unscheduled and not unrolled b. Scheduled and not unrolled c. Scheduled and minimally unrolled code to have zero stalls Clearly mention how many times you unrolled the loop to obtain zero stalls. FO, O(R2) SUB.D F1, FO, F4 DIV.D F5, F1, F6 ADD.D F3, FO, F2 Loop: L.D // F4 contains a scalar constant // F6 contains a scalar constant // F2 contains a scalar constant F3, 0(R2) DADDI R2, R2, 8 S.D DADDI R4, RS, R6 DADDI R1, R1, -8 BNEZ R1, Loop
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