Systems Architecture
7th Edition
ISBN: 9781305080195
Author: Stephen D. Burd
Publisher: Cengage Learning
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Chapter 4, Problem 3PE
Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses.
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1. Anna designs a 2.5 GHz processor where two important programs, A and B, take onesecond each to execute. Each program has a CPI of 1.25. Elsa is tasked with designingthe company's next-generation processor and she comes up with an idea that improvesthe CPI of A to 1.1 and the CPI of B to 0.9. But the idea is so complex that theprocessor can only be implemented with a cycle time of 0.5 ns. Does Elsa's newprocessor out-perform Anna's processor on program A? How about on program B?2. Consider two different implementations of the same instruction set architecture. Theinstructions can be divided into four classes according to their CPI (class A, B, C, andD). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a clockrate of 3 GHz and CPIs of 1, 2, 2, and 2.Given a program with a dynamic instructioncount of 106 instructions divided into classes as follows: 10% class A, 20% class B,50% class C, and 20% class D, which is faster: P1 or P2?
A complete 6-stage non-pipelined 16-bit CPU architecture include 6 components: a register file, a decoder, an ALU, a control unit, a program counter, and ram/memory.
Brief overview:
opcode is 4 bits
14 different instructions implemented
8 general purpose registers
RRR-type instructions are the largest, and take up 9 bits in register addresses
1 bit is a condition bit
2 bits unused
simulated clock runs at a 10ns period or 100Mhz
simulated memory is 512 bytes
Referring to the 3 components as in the picture, namely the File Register, Decoder and ALU, you are required to describe how the three components operate.
Chapter 4 Solutions
Systems Architecture
Ch. 4 - Prob. 1VECh. 4 - ________________ generates heat in electrical...Ch. 4 - Prob. 3VECh. 4 - Prob. 4VECh. 4 - Prob. 5VECh. 4 - One _________________ is one cycle per second.
Ch. 4 - Prob. 7VECh. 4 - When an instruction is first fetched from memory,...Ch. 4 - Prob. 9VECh. 4 - Prob. 10VE
Ch. 4 - Prob. 11VECh. 4 - Prob. 12VECh. 4 - The contents of a memory location are copied to a...Ch. 4 - Prob. 14VECh. 4 - A(n) ________________ instruction always alters...Ch. 4 - Prob. 16VECh. 4 - A(n) ____________________ instruction copies data...Ch. 4 - The CPU incurs one or more _________________ when...Ch. 4 - The CPU incurs one or more _____ when its idle,...Ch. 4 - In many CPUs, a register called the _____ stores...Ch. 4 - The components of an instruction are its _____ and...Ch. 4 - Two 1-bit values generate a 1 result value when...Ch. 4 - A(n) _____ operation transforms a 0 bit value to 1...Ch. 4 - _____ predicts that transistor density will double...Ch. 4 - A(n) _____ is a measure of CPU or computer system...Ch. 4 - _____ is a CPU design technique in which...Ch. 4 - Describe the operation of a MOVE instruction. Why...Ch. 4 - Prob. 2RQCh. 4 - Prob. 3RQCh. 4 - Prob. 4RQCh. 4 - Prob. 5RQCh. 4 - Prob. 7RQCh. 4 - Prob. 8RQCh. 4 - Prob. 9RQCh. 4 - How does pipelining improve CPU efficiency? What’s...Ch. 4 - Prob. 11RQCh. 4 - Develop a program consisting of primitive CPU...Ch. 4 - If a microprocessor has a cycle time of 0.5...Ch. 4 - Processor R is a 64-bit RISC processor with a 2...Ch. 4 - Prob. 4PECh. 4 - Prob. 1RPCh. 4 - Prob. 2RPCh. 4 - Prob. 3RP
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