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We will be implementing a new instruction within the MIPS architecture. New instruction will decremnent a Variable stored in a memory location and store the decremented value in a register (Rt). This new instruction will be called DECR. Its usage and interpretation is Usage: DECR Offset(4*Rs),Rt Interpretation: Reg[Rt]= Mem[4*Rs+Offset] - 1 Which blocks are used and which control signals are generated for this instruction. How would the Instruction code fields look like ? Do we need to add an extra hardware logic, explain ? (You may draw a simplified datapath flow)

We will be implementing a new instruction within the MIPS architecture. New instruction will decremnent a Variable stored in a memory location and store the decremented value in a register (Rt). This new instruction will be called DECR. Its usage and interpretation is Usage: DECR Offset(4*Rs),Rt Interpretation: Reg[Rt]= Mem[4*Rs+Offset] - 1 Which blocks are used and which control signals are generated for this instruction. How would the Instruction code fields look like ? Do we need to add an extra hardware logic, explain ? (You may draw a simplified datapath flow)

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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REFERENCES: PPV- Add result Shift loft 2 RegDat Branch Memike MenoReg Control ALUOP Instruction (31-20] ALUSIC Regite Instruction (25-21) Road register 1 Road Read register 2 Raad PC address data 1 nstruction (20-101 Instruction 31-0) ALU ALU result Read data Address Write register Reag data 2 Instruction momory nstruction [15-111 Write dala Registors Wrte Data data me mory invstruction (150) 16 Sign- 32 l extond ALU control Instruction (5-0 PCSrc Add ALU Addrosult Shift left 2 RegWrite Instruction (25:21) Read address Read register 1 Read PC MomWrite Instruction [20:16] Read data 1 register 2 ALUSIC MemtoRag Instruction 31:0) Zero ALU ALU Read Address data Writo Read result Instruction memory Instruction [15.11) register data 2 M. Write data Registers RagDet Data Write e memory data Instruction (15:0) 16 32 Sign- extond ALU contrei Memead Instruction (5.0j ALUOD
Transcribed Image Text:REFERENCES: PPV- Add result Shift loft 2 RegDat Branch Memike MenoReg Control ALUOP Instruction (31-20] ALUSIC Regite Instruction (25-21) Road register 1 Road Read register 2 Raad PC address data 1 nstruction (20-101 Instruction 31-0) ALU ALU result Read data Address Write register Reag data 2 Instruction momory nstruction [15-111 Write dala Registors Wrte Data data me mory invstruction (150) 16 Sign- 32 l extond ALU control Instruction (5-0 PCSrc Add ALU Addrosult Shift left 2 RegWrite Instruction (25:21) Read address Read register 1 Read PC MomWrite Instruction [20:16] Read data 1 register 2 ALUSIC MemtoRag Instruction 31:0) Zero ALU ALU Read Address data Writo Read result Instruction memory Instruction [15.11) register data 2 M. Write data Registers RagDet Data Write e memory data Instruction (15:0) 16 32 Sign- extond ALU contrei Memead Instruction (5.0j ALUOD
:- We will be implementing a new instruction within the MIPS architecture. New instruction will decrement a Variable stored in a memory location and store the decremented value in a register (Rt). This new instruction will be called DECR. Its usage and interpretation is Usage: DECR Offset(4*Rs),Rt Interpretation: Reg[Rt]= Mem[4*Rs+Offset] - 1 Which blocks are used and which control signals are generated for this instruction. How would the Instruction code fields look like ? Do we need to add an extra hardware logic, explain ? (You may draw a simplified datapath flow)
Transcribed Image Text::- We will be implementing a new instruction within the MIPS architecture. New instruction will decrement a Variable stored in a memory location and store the decremented value in a register (Rt). This new instruction will be called DECR. Its usage and interpretation is Usage: DECR Offset(4*Rs),Rt Interpretation: Reg[Rt]= Mem[4*Rs+Offset] - 1 Which blocks are used and which control signals are generated for this instruction. How would the Instruction code fields look like ? Do we need to add an extra hardware logic, explain ? (You may draw a simplified datapath flow)
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