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- Q1) For the circuits shown in figures 1 and 2: 1. What is the function of output? 2. Find the max. and min. Vol. value? 3. Determine the static power (avg.)? 4. Design equivalent logic circuit by CMOC logic circuits? Use VDD= 10 V. Vr.o=1V. Vru-1V. (W/L)o= (5/2), (W/L)L (20/2), RD = 40k, KL = 10P A/V^2 and KO = 40pA/V`2? Figure 1 5 VDD RD Figure 2 बदना देQ2/A) Design 8x1 multiplexer using 2x1 multiplexer? Q2 B)Simplify the Logic circuit shown below using K-map then draw the Simplified circuit? Q2/C) design logic block diagram for adding 12 to 5 using full adder showing the input for each adder?Design a logic circuit for decoder that accepts 3-bit input and displays alphabet “048” at the seven- segment as illustrated at Figure 1 (a). The input-output mapping shown in Table 1 (a). Refer Figure 1(b) and Figure 1(c) for seven-segment display format showing arrangements of segments using common anode connection. Show each steps clearly to produce the expressions and required design. [Rekabentuk litar logik untuk penyahkod yang menerima input 3-bit dan paparkan abjad "048" di tujuh-segmen seperti digambarkan pada Rajah 1(a). Pemetaan masukan-keluaran ditunjukkan dalam Jadual 1(a). Rujuk Rajah 1(b) and Rajah 1(c) untuk format paparan tujuh-segmen yang menunjukkan susunan segmen menngunakan sambungan 'common anode'. Tunjukkan setiap langkah dengan jelas untuk menghasilkan ungkapan dan reka bentuk yang dikehendaki.] Xs X6 X7 DECODER Figure 1(a) [Rajah 1(a)] a b с d e f g a 80123456789 Figure 1(c) [Rajah 1(c)] g Figure 1 (b) [Rajah 1(b)] b с DP
- Q1/ Draw the logic circuit after simplify the circuit show below using K. map: A Y. C- Add filo B.answere fast please question from DIGITAL LOGIC DESIGN TOPIC : Designing Combinational Logic You are designing a water level circuit using 74ALS151 (8 to 1 Multiplexer IC)* When input is 0000 that means tank is empty.* When input is 1111 that means tank is full.* When input is below 5, that means water level is low.* So, make a circuit using 74ALS151 Multiplexer IC that shows a "low water" indicator light(by setting an output L to 1) when the water level drops below level 5.An X-input exclusive-OR gate and a Y-input exclusive-OR gate (where X=3, Y=4 have their outputs connected to a 2-input exclusive-NORgate. Do the following:a) Draw the logic diagram and analyze the logic expression of the output (in standard SOPform).b) List out all essential prime implicants.
- ) The input waveforms in are applied to logic circuit in figure below. Determine the output waveforms. B G2 C C D D E(c) Figure Q3(c)(i) shows a register and Figure Q3(c)(ii) shows the input waveforms (CLOCK and Data in) to the circuit. A1 A9 A10 A2 Function generator A3 A11 A12 AS A13 A6 A14 A7 A15 Data in Bop.7) ip.r 82p.7) Logic analyser U1 U2 U3 U4 UO 6. 1. 6 1 6 INVERTER 3 CLK 3 CLK oCLK CLK 5 K K 5 K K 4027 Clock Function generator Figure Q3(c)(i) (i) Determine the type of register as shown in Figure Q3(c)(i).Draw logic diagram for half adder and full adder circuit using Logisim Software
- subject: Digital Logic &Design Q: Describe the operation of a basic parity generating and checking logicPalagiaph 1. Find logic finctions for the circuits shown below. FQ5 (a) Discuss, the major dıfferences between ticld programmable gatc arrays (FPGAS) and programmable logie devices (PLDS. where an FPGA may be approprate in a streamıng TV system. Simple multiplexers can be used to mimic a number of two-input logic functions by appropriate mapping of nputs X X, and SEL Show how the multiplexer shown in figure Q5a can be used to perform the function F= AOB (b) SEL Figure Q5a Figure Q5b (over) shows the schematic of a Xilinx 3000 sennes logic cell M Label the configuration bits of the various multiplexers n the celL with zeroed configuration bits selecting the topmost input to each multuplexer. Each multiplexer has -2 ns, the combinatorial loge block is guaranteed to have WS7 ns, and the D-type flip-flops have t4 ns and r 1 ns (c) We wish to construct a two-bit counter from this logie cell. where Q, and Q are the high and low order outputs of the counter, CLK is the clock signal, AR is an asynchronous reset signal, EN enables the counter, and LD allows…