3) Reduce (Simplify) the logic circuit expression A BU
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- Digital Logic Design Results should be in Tabulated form. Explanation of the resultsFigure Q2(e) shows a programmable logic array (PLA) unit with two inputs, four columns, and three outputs. Show the steps to implement a one-bit comparator using this PLA. Note that the output should have equal (EQ), less than (LT), and greater (GT) status. A, 02 Figure Q2(e)6. For the follow logic circuit system, the output f is: 5 (A) ab. (B) a + b. (C) a'+b'. (D) a'b'. a b
- USE DIGITAL LOGIC AND DESIGNDesign the following combinational logic circuit with a four-bit input and a three-bit output. The input represents two unsigned 2-bit numbers: A1 A0 and B1 B0. The output C2 C1.C0 is the result of the integer binary division A1 A0/B1 B0 rounded down to three bits. The 3-bit output has a 2-bit unsigned whole part C2 C1 and a fraction part CO. The weight of the fraction bit CO is 21. Note the quotient should be rounded down, i.e. the division 01/11 should give the outputs 00.0 (1/3 rounded down to 0) not 00.1 (1/3 rounded up to 0.5). A result of infinity should be represented as 11.1. A minimal logic implementation is not required. (Hint: start by producing a truth table of your design).Draw the logic circuit for the simplified expression a) and b)
- .Provide a detailed report on the combinational logic circuits below. 1. Magnitude Comparators a. What are magnitude comparators? b. How does it work? c. Applications of magnitude comparators.Draw logic diagram for half adder and full adder circuit using Logisim Software) The input waveforms in are applied to logic circuit in figure below. Determine the output waveforms. B G2 C C D D E