Problem 3: If we assume a CPU can process 100000 Instruction/sec. Compute the CPU utilization in the following scenarios (program 1000 instructions in average): a) Program instructions are stored in the main memory with access speed 1000 Instruction/sec. b) Program instructions are stored in the cache memory with access speed 50000 Instruction/sec.

Problem 3: If we assume a CPU can process 100000 Instruction/sec. Compute the CPU utilization in the following scenarios (program 1000 instructions in average): a) Program instructions are stored in the main memory with access speed 1000 Instruction/sec. b) Program instructions are stored in the cache memory with access speed 50000 Instruction/sec.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Answer the following questions. A. A computer system has a main memory access time as 60ns. you as a computer organization expert has been asked to reduce the memory access time to 20ns by adding a suitable cache. Assume that the miss probability is 10%. What should be the fastness of cache (in terms of access time) for this requirement? B. Consider the instruction ADD R1, X, which adds the contents of location X from the contents of register R1, and places the result in R1. Show the micro-operations used during fetch and execution phase of the instruction.
(15pt) Assume that instruction cache miss rate is 2%, data cache miss rate is 10%, CPI (clock cycle per instruction) is 2 without any memory stall, and miss penalty is 100 cycles. In addition, assume that the frequency of loads/stores is 30%. (a) Compute CPI with memory stall. (b) When CPI without any memory stall becomes 1, compute CPI with memory stall. (c) If the CPU clock rate is doubled with the same memory when CPI without memory stall is 2, compute CPI with memory stall.
1. When a program is adapted to run on multiple cores in a multiprocessor system, the execution time on each core is comprised of computing time and the overhead time required for locked critical sections and/or to send data from one core to another. Assume a program requires t = 200 sec of execution time on one core. When run on n cores, each core requires t/n sec, as well as an additional 10 sec of overhead, irrespective of the number of cores. a. Compute the per-core execution time for 2, 4, 8, 16, 32, 64, and 128 cores. b. For each case, list the corresponding speedup relative to a single core and the ratio between actual speedup versus ideal speedup (speedup if there was no overhead).
Consider a processor running a program. 30% of the instructions of which require a memory read or write operation if the cache bit ratio is 0.95 for instructions and 0.9 for data. When a cache bit occurs for instruction or for data, only one clock is needed while the cache miss penalty is 17 clocks to read/write on the main memory. Work out the time saved by using the cache, given the total number of instructions executed is 1 million.
If a processor has a CPI of 2 without any memory stalls, and the miss penalty is 100 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed in the following two scenarios. Assume the frequency of all loads and stores is 30%. a) Miss rate of an instruction cache is 2% and the miss rate of data cache is 5% b) Miss rate of an instruction cache is 1% and the miss rate of data cache is 2%.
For the same instruction being executed: add $s1, $s2, $t0 using the following delays for each block/action: Decode + Register File Read Data Memory Access Instruction Register Read ALU (all Register Mux Memory Access operations) Write 25 200 |125 150 300 25 10 But, now assume that all types of instructions have to be executed in one clock cycle, not just the 'add' instruction. What is the minimum clock cycle from the times below which will suffice as the clock cycle time to run the microprocessor at? Choose the best answer. 845 535 545 835
The memory access time is I nanosecond for read operation with a hit in cache. * nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 anoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions is
Multicycle execution is better than single cycle execution since it is: a. Every operation is completely carried out within a single clock cycle b. Break up operation so that each stage is executed in 1 clock cycle and allow skipping of unused stages. c. The maximum clock frequency is determined by the slowest instruction in the instruction set. d. A form of parallelism since more than one instruction is executed by the processor in any given cla
Consider a program containing ‘j’ instructions of which ‘k’ instructions are loop instructions. The program is executed on a system that contains cache. Instruction fetch from memory costs ‘l’ nano-second while that for cache costs ‘m’ nano-second. If loop is executed ‘n’ times and every other instruction is executed once only, a) derive an expression for the speedup due to use of cache (ratio of the program execution time without cache to the program execution time with cache). Assume, cache is empty initially and is large enough to hold the loop completely and all the data required by the program is hard-coded in the program. b) If j = 1500, k = (your registration number), l = 20 nano-seconds , m = 2 nano-seconds, and n = 100 calculate the speedup using your expression derived in ‘a’ part.
On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
Problem 4. There are two levels L1 and L2 of caches. L1 has hit rate 95%, and L2 has hit rate 80%. L1 has I cycle to access. L2 has 20 cycles to access. Memory has 400 cycles to access. Ignoring memory access clocks per instruction (CPI) has 1 cycle. Assume that 40% instruction has data access. Compute the CPI that includes memory access. You need to consider that there is a memory access to fetch each instruction.
6. Assume you have an instruction cache miss rate of 2%, and a data cache miss rate of 6%. The miss penalty is 100 cycles. You have a program that is 30% load-store instructions, with a base CPI of 1. What will its CPI be including cache misses?