BNE LOOPO How many clock cycles are required to complete the execution of the above code on non- pipelined processor assuming each instruction will take 1 cycle to execute completely? Show calculations. How many clock cycles required to complete the execution of the above code on 3-staged pipelined processor? Draw the pipeline diagram for the same. Let one stage requires one clock cycle and assume all memory references hit in cache.

Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter4: Processor Technology And Architecture
Section: Chapter Questions
Problem 15VE: A(n) ________________ instruction always alters the instruction execution sequence. A(n)...
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1A. Consider the following code:
AREA ASCENDING, CODE, READONLY
ENTRY
MOV R8, #2
LOOPO LDR R1, [R2], #4
STR R1, [R3], #4
SUBS R8, R8, #1
CMP R8, #0
BNE LOOPO
How many clock cycles are required to complete the execution of the above code on non-
pipelined processor assuming each instruction will take 1 cycle to execute completely? Show
calculations.
How many clock cycles required to complete the execution of the above code on 3-staged
pipelined processor? Draw the pipeline diagram for the same. Let one stage requires one clock
cycle and assume all memory references hit in cache.
Transcribed Image Text:1A. Consider the following code: AREA ASCENDING, CODE, READONLY ENTRY MOV R8, #2 LOOPO LDR R1, [R2], #4 STR R1, [R3], #4 SUBS R8, R8, #1 CMP R8, #0 BNE LOOPO How many clock cycles are required to complete the execution of the above code on non- pipelined processor assuming each instruction will take 1 cycle to execute completely? Show calculations. How many clock cycles required to complete the execution of the above code on 3-staged pipelined processor? Draw the pipeline diagram for the same. Let one stage requires one clock cycle and assume all memory references hit in cache.
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