The following code is to be scheduled and executed on a two-slot VLIW machine with the goal of achieving a minimum number of cycles. A bundle in this architecture has two instructions. The first of these instructions can be only an ALU or branch instruction, whereas the second one can be only a load or sto instruction. You are allowed to reorder independent instructions and change the offset of addressing (if needed). You are not allowed to combine instruction loop: Iw r2, 0(r1) Iw r4, 4(r1) add r2, r2, r8 add r4, r4, r8 sw r2, 4(r1) sw r4, 0(r1) sub r1, r1, -4 bne r1, $zero, loop Show the instruction bundles issued by the VLIW machine for the above code. Please write one instruction bundle per line.

The following code is to be scheduled and executed on a two-slot VLIW machine with the goal of achieving a minimum number of cycles. A bundle in this architecture has two instructions. The first of these instructions can be only an ALU or branch instruction, whereas the second one can be only a load or sto instruction. You are allowed to reorder independent instructions and change the offset of addressing (if needed). You are not allowed to combine instruction loop: Iw r2, 0(r1) Iw r4, 4(r1) add r2, r2, r8 add r4, r4, r8 sw r2, 4(r1) sw r4, 0(r1) sub r1, r1, -4 bne r1, $zero, loop Show the instruction bundles issued by the VLIW machine for the above code. Please write one instruction bundle per line.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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