5. Pipelined datapath has five stages, ie., instruction fetch (IF), decode (ID), execution (EX), memory(MEM), and write back (WB). It has a hazard detection unit. An instruction will be stalled at thedecode stage if any of its operands isn't ready. Consider executing the following code on this datapath(1) At the end of fifth cycle of execution, what instruction will be in each of the pipelinestages? (If there is any "bubble" in the pipeline, please write "NOP" in thecorresponding pipeline stage.) (5%)You must write the answer with the following format.instructionIFinstructionlw $r2, 10($1)sub $r4, $13, Sr2add $r5, Sr6, $7and Sr8, Sr4,$r5IFIDEX(2) If the datapath has a forwarding unit to resolve the data hazard, what instruction will be ineach of the pipeline stages at the end of the fifth cycle? (If there is any "bubble" in the-pipeline, please write "NOP" in the corresponding pipeline stage.) (5%)You must write the answer with the following format:(DMEMEXWB.MEMWR

Given InstructionsI1: lw $r2, 10($r1)I2: sub $r4, $r3, $r2I3: add $r5, $r6, $r7I4: and $r8, $r4,…

He stage if any of its operands isn't ready. Consider executing the followi lw $r2, 10($1) sub $r4, $r3, Sr2 add $r5, $r6, $7 and $r8, Sr4,$r5 At the end of fifth cycle of execution, what instruction will be in each of

He stage if any of its operands isn't ready. Consider executing the followi lw $r2, 10($1) sub $r4, $r3, Sr2 add $r5, $r6, $7 and $r8, Sr4,$r5 At the end of fifth cycle of execution, what instruction will be in each of

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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7. In a normal branch instruction, we provide the number of instructions we need to go to with respect to the current Program Counter. We want to modify this in the datapath. Suppose, instead of providing the number of instructions, we provide it 16-bit address, which when sign extended to 32 bits and then add 8 to it, will provide the exact address to branch to, what modifications will you make in the datapath below to accommodate it.
Flags register in microprocessor are used extensively in programming (low level) to test a condition. For example, to test whether the previous instruction is making the accumulator zero, zero flag can be tested. If a flag register is made up of 16 bits, with 9 flags. Six of the flags are status flags and three are control flags. With your knowledge in microprocessor flag register, how would you: i) Identify this flag register and design it complete flag.4 ii) Show the functions of the represented bits in the register.
The instruction “addi” is an I-type instruction that can be executed using the Single-cycle datapath without modification. Answer the following question: (a) Give values of all control signals needed to execute this instruction on the single-cycle data. For example: addi $t2, $S2, 3.
D-Latch is a simple clocked memory element in which the output is equal to the stored state inside the element. In D-Latch the state is changed whenever the appropriate inputs change and the clock is asserted. A D-Latch has two inputs and two outputs. The inputs are the data value to be stored and a clock signal that indicates when the latch should read the value on the data input and store it. The outputs are simply the value of the internal state and its complement. When the clock input is asserted, the latch is said to be open, and the value of the output becomes the value of the data input. When the clock input is de-asserted, the latch is said to be closed, and the value of the output is whatever value was stored the last time the latch was open. What is the difference between DFF and D-Latch? Can one chip be used for constructing the other? Explain.
Q2. Refer to datapath design on slide no. 26 with added blocks for jump instructions as shown inslide 33 in Chapter 4 (part 1). Let’s assume a program has 500 instructions. These instructions aredistributed as follows:R-Type Immediatearithmetic(addi)Load Store Branch Jump25% 5% 20% 20% 10% 20%Answer the following questions (show calculations):a) How many instructions will use instruction memory?b) How many instructions will use data memory?c) How many instructions will use the sign extend block?d) In the clock cycles, where the sign extend block is not required, does it remain idle? If yes,how? If not, what happens to the output of the block in that cycle? chapter 4, slide 33 is added as an image needed to solve the question
Multiple Choice An 'instruction fetch/read' results in three sets of numbers that go to the Registers Block as studied in class. These three numbers in the instruction represent bits 25-21 for 'Read Register 1', bits 20-16 for 'Read Register 2', and bits 15-11 for the 'Write Register'. What does the 5 bits width of each of these indicate? Choose the best answer. Group of answer choices That there are 15 registers that can be addressed in this architecture That each word is 32 bits long That there are 32 registers that can be addressed in this architecture That the word is 15 bits long in this architecture
use: Microchip Studio and ATmega328p Activity 3: COM instruction flags Write and assemble the following program. COM instruction can trigger Z(Zero), C(Carry), N(Negative), and V(Overflow) flags. Use the simulator to single-step and examine the flags and register content after the execution of each flag triggering instruction. LDI LDI LDI LDI R20,0 R21, 0xFF R22, 0x11 R23, 0x22 COM R20 COM R21 COM R22 COM R23 End: RJMP End R20 → R21 → R22: = → R23 = [Hex], Active Flags: [Hex], Active Flags: [Hex], Active Flags: [Hex], Active Flags:
In an instruction cycle the execute phase includes Select one: a.the operation of the decoded instruction on all the operands. b.there is no correct answer here c.incrementing the program counter by 2 addresses. d.the step of decoding the instruction for execution. e.the transfer of the content of memory address pointed by the program counter.
6. Suppose that the interrupt processing method of is to store the breakpoint in the address of 00000Q unit, and fetch the instruction from the 77777Q unit (that is the first instruction of the interrupt service routine) and execute it. Write the micro-operations sequence that completes this function.
BX=FFFF, after instruction INC BX is executed, CF ||
5. Below is a depiction of a loop in instruction memory address Охо TOP: instruction 1 Ox4 instruction 2 Ox8 instruction 3 OxC instruction 4 Ох10 conditional branch to TOP Assume that the branch target buffer is initially empty, and the prediction bits are set to Strongly Taken (ST). Fill in the blanks On the first pass through the loop we take the branch. The branch target bits are now We suffer stalls. On the second pass through the loop we don't take the branch. The branch target bits are now We suffer stalls. On the third pass through the loop we don't take the branch. The branch target bits are now We suffer stalls. On the fourth pass through the loop we don't take the branch. The branch target bits are now We suffer stalls.
An instruction at address 021 in the basic computer has I = 0, an operation code of the AND instruction, and an address part equal to 083 (all numbers are in hexadecimal). The memory word at address 083 contains the operand B8F2 and the content of AC is A937. Go over the instruction cycle and determine the contents of the following registers at the end of the execute phase: PC, AR, DR, AC, and IR. Repeat the problem six more times starting with an operation code of another memory-reference instruction. 5-10.