Design a 3-Bit (fixed reference) comparator for 100 reference values. b) Logic Gates c) PROM d) PAL
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Design a 3-Bit (fixed reference) comparator for 100 reference values.
b) Logic Gates
c) PROM
d) PAL
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- Figure 4 shows the decimal to BCD encoder logic. Assume that the 9 input and 3 inputare both HIGH.i) Determine the output code.ii) Is the value valid for BCD (8421) code?6. i) For the circuit shown in Figure Q16, Find the logic functions of X and Y Figure Q1 ii) Simplify X and Y using Boolean algebra. hp ort deleteA d. B Figure 1 3. Referring to the logic circuit in Figure 1, determine: a. The simplified Boolean expression. b. The output waveform. C H c. Due to fabrication errors, lines d and f were shorted to the supply voltage. What happens to the output of the circuit? d. Your hardware resources are limited to 2-input NOR gate only. Draw the gate schematic of the simplified Boolean expression in 3(a).
- logic circuit diagram for fabinaaci counter that gives output in fabinaaci sequence.upto 2 digits please mentions the gates and ics used in circuit.Q2/A) Design 8x1 multiplexer using 2x1 multiplexer? Q2 B)Simplify the Logic circuit shown below using K-map then draw the Simplified circuit? Q2/C) design logic block diagram for adding 12 to 5 using full adder showing the input for each adder?d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.
- ) The input waveforms in are applied to logic circuit in figure below. Determine the output waveforms. B G2 C C D D EQ1// What are the difference between Logic Devices and Programmable Logic Devices? Q2// Explain the advantage's of Programmable Logic Devices? Q3// List the disadvantages of Fixed function logic devices. Q4// Compare between Logic Devices and Programmable Logic Devices?Q4(a) Adder is divided into three types which are half adder, full adder, and parallel adder. Illustrate the implementation of full adder using half adder with necessary logic gates. (i) (ii) Figure Q4(a)(ii) shows the input timing diagram for a full adder. Illustrate the timing diagrams for output S and Cout- Cin Cout Figure Q4(a)(ii)
- Q4(a) Adder is divided into three types which are half adder, full adder, and parallel adder. Illustrate the implementation of full adder using half adder with necessary logic gates. (i) (ii) Figure Q4(a)(ii) shows the input timing diagram for a full adder. Illustrate the timing diagrams for output S and Cout- B Cin Cout Figure Q4(a)(ii) (iii) Given A = 111001 and B = 100010. Construct a 6-bit parallel adder to solve for A + B.Q1) For the circuits shown in figures 1 and 2: 1. What is the function of output? 2. Find the max. and min. Vol. value? 3. Determine the static power (avg.)? 4. Design equivalent logic circuit by CMOC logic circuits? Use VDD= 10 V. Vr.o=1V. Vru-1V. (W/L)o= (5/2), (W/L)L (20/2), RD = 40k, KL = 10P A/V^2 and KO = 40pA/V`2? Figure 1 5 VDD RD Figure 2 बदना देDerive the state table and the state graph for the following logic circuit: A' B' B DA Clock Clock X B'