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- Q2/A) Design 8x1 multiplexer using 2x1 multiplexer? Q2 B)Simplify the Logic circuit shown below using K-map then draw the Simplified circuit? Q2/C) design logic block diagram for adding 12 to 5 using full adder showing the input for each adder?The diagram shows a transistor used to interface a logic gate to a lamp for it to be fully lit. Resistance of lamp=80 ohms 9Vo Signal from logic gate Ovo R Logic gate Output 0.2V 3.3V IB V₁ Lamp a) The logic gate outputs 0.3 for logic 0,and 3.3V for logic 1. Complete the table below to show the effect of these signals on the transistor and lamp by: i) Adding the correct voltages to the V1 column ii)writing either 'Off' or On to show the state of the lamp V1(V) same as VB When filly lit the, the lamp passes a current of 100mA. The transistor has a current gain, beta ẞ of 60 b)Calculate the base current, IB. c)Using KVL find the voltage drop across R. Sate of lampA logic gate switches in 5ns and has a triangular shoot through current with a peak value of 8mA. Estimate the value of nearby decoupling capacitor required to limit the power supply noise due to switching to 150mV. Enter your answer in pF to 3 significant figures.
- (a) Consider the flipflop circuits below: (i) Name the 2 circuits given in the figure. Explain how they are different from each other. a. b. (ii) Choose from the list the input that triggers data to travel to the next flipflop in a counter. A: Input at top NAND gate B: Input at bottom NAND gate C: Clock input clk Q5) Draw the circuit diagram using diode and write the truth table of a logic gates whose output will be the logical OR operation of two inputs.It's expected to construct one of the listed circuits and answer the relevant questions. 1. Design and implementation of combinational circuit using K-map and logic gate. 2. Design and analysis of combinational circuits as Adder & Subtractor / Multiplexer & De- multiplexer.
- logic circuit diagram for fabinaaci counter that gives output in fabinaaci sequence.upto 2 digits please mentions the gates and ics used in circuit.The gate of a JFET is . . biased Select one: a. forward b. reverse as well as forward c. none of the above d. reverse) The input waveforms in are applied to logic circuit in figure below. Determine the output waveforms. B G2 C C D D E
- A certain digital circuits designed to operate with voltage levels of -0.2Vdc and -3.0Vdc. If H= 1 =-0.2 Vdc and L =0 =-3.0 Vdc, is this positive logic or negative logic ? H=+5.0Vdc. and. L=+1.0Vdc What are the voltage levels between fall and rise times are measured? What is the value of Duty cycle H if the waveform is high for 2 ms and low for 5 ms?3. Refer chapter -5 a) What are different logic families that fall under bipolar families? b) With neat diagram explain 2 input NAND operation using DTL logic. c) Explain with neat diagram DAC circuit using Op Amp and binary weighted resisters.What are the values of the inputs a, b, c, d, e, f and g for a Seven-Segment LED that displays the number 2? Assume active high logic. a) 1101101 b) 1010101 c) 1101110 d) None of the above e) All of the above