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E(t)=u(t) | num(z) 20 den(z) s2+9s+20 Plant Zero-Order Digital Controller Hold Fig. 2 A closed-loop sampled-data system with digital controller Y(t) 1. The simulink model for a closed-loop sampled-data system is given in Fig. 1. 20 E(t)=u(t) +9s+20 Zero-Order Hold Plant Y(t) Fig. 1 A closed-loop sampled-data system a) Before the experiment, calculate the transfer function of the system that is given in Fig. 1. Find T, S, W, P.O, and ts. Also, calculate the steady-state error for unit-step input. Assume that zero-order hold reconstruction method is used and the sampling time will be 0.1 second (T = 0.1 sec). b) Plot the step response of the system. Observe the P.O and ts from the figure. Use "damp" command to find the c and W. Compare the results with a. c) Design a unity-dc-gain phase-lag compensator that yields a phase margin of 50 degree. d) Start simulink and construct the model that is given in Fig.2. Additionally, in order to plot the Y(t) by using workspace use a clock and a workspace blocks which are named as t, ytSampled. Set the sampling time -1 for all workspace blocks. Use the result of e for Digital Controller. Select an appropriate time for simulation and run it by clicking on the start button. e) Plot the Y(t) by using t and ytSampled. Compare the results with a and b. f) Repeat c, d, and e for de-gain values are 10,100, and 1000. g) Discuss the effect of the phase-lag compensator for different de-gain values (Hint: Consider both the transient and steady-state responses). Does the increment in the de-gain destabilize this system? Explain your answer by proving the mathematical expressions.

E(t)=u(t) | num(z) 20 den(z) s2+9s+20 Plant Zero-Order Digital Controller Hold Fig. 2 A closed-loop sampled-data system with digital controller Y(t) 1. The simulink model for a closed-loop sampled-data system is given in Fig. 1. 20 E(t)=u(t) +9s+20 Zero-Order Hold Plant Y(t) Fig. 1 A closed-loop sampled-data system a) Before the experiment, calculate the transfer function of the system that is given in Fig. 1. Find T, S, W, P.O, and ts. Also, calculate the steady-state error for unit-step input. Assume that zero-order hold reconstruction method is used and the sampling time will be 0.1 second (T = 0.1 sec). b) Plot the step response of the system. Observe the P.O and ts from the figure. Use "damp" command to find the c and W. Compare the results with a. c) Design a unity-dc-gain phase-lag compensator that yields a phase margin of 50 degree. d) Start simulink and construct the model that is given in Fig.2. Additionally, in order to plot the Y(t) by using workspace use a clock and a workspace blocks which are named as t, ytSampled. Set the sampling time -1 for all workspace blocks. Use the result of e for Digital Controller. Select an appropriate time for simulation and run it by clicking on the start button. e) Plot the Y(t) by using t and ytSampled. Compare the results with a and b. f) Repeat c, d, and e for de-gain values are 10,100, and 1000. g) Discuss the effect of the phase-lag compensator for different de-gain values (Hint: Consider both the transient and steady-state responses). Does the increment in the de-gain destabilize this system? Explain your answer by proving the mathematical expressions.

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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E(t)=u(t) | num(z) 20 den(z) s2+9s+20 Plant Zero-Order Digital Controller Hold Fig. 2 A closed-loop sampled-data system with digital controller Y(t)
Transcribed Image Text:E(t)=u(t) | num(z) 20 den(z) s2+9s+20 Plant Zero-Order Digital Controller Hold Fig. 2 A closed-loop sampled-data system with digital controller Y(t)
1. The simulink model for a closed-loop sampled-data system is given in Fig. 1. 20 E(t)=u(t) +9s+20 Zero-Order Hold Plant Y(t) Fig. 1 A closed-loop sampled-data system a) Before the experiment, calculate the transfer function of the system that is given in Fig. 1. Find T, S, W, P.O, and ts. Also, calculate the steady-state error for unit-step input. Assume that zero-order hold reconstruction method is used and the sampling time will be 0.1 second (T = 0.1 sec). b) Plot the step response of the system. Observe the P.O and ts from the figure. Use "damp" command to find the c and W. Compare the results with a. c) Design a unity-dc-gain phase-lag compensator that yields a phase margin of 50 degree. d) Start simulink and construct the model that is given in Fig.2. Additionally, in order to plot the Y(t) by using workspace use a clock and a workspace blocks which are named as t, ytSampled. Set the sampling time -1 for all workspace blocks. Use the result of e for Digital Controller. Select an appropriate time for simulation and run it by clicking on the start button. e) Plot the Y(t) by using t and ytSampled. Compare the results with a and b. f) Repeat c, d, and e for de-gain values are 10,100, and 1000. g) Discuss the effect of the phase-lag compensator for different de-gain values (Hint: Consider both the transient and steady-state responses). Does the increment in the de-gain destabilize this system? Explain your answer by proving the mathematical expressions.
Transcribed Image Text:1. The simulink model for a closed-loop sampled-data system is given in Fig. 1. 20 E(t)=u(t) +9s+20 Zero-Order Hold Plant Y(t) Fig. 1 A closed-loop sampled-data system a) Before the experiment, calculate the transfer function of the system that is given in Fig. 1. Find T, S, W, P.O, and ts. Also, calculate the steady-state error for unit-step input. Assume that zero-order hold reconstruction method is used and the sampling time will be 0.1 second (T = 0.1 sec). b) Plot the step response of the system. Observe the P.O and ts from the figure. Use "damp" command to find the c and W. Compare the results with a. c) Design a unity-dc-gain phase-lag compensator that yields a phase margin of 50 degree. d) Start simulink and construct the model that is given in Fig.2. Additionally, in order to plot the Y(t) by using workspace use a clock and a workspace blocks which are named as t, ytSampled. Set the sampling time -1 for all workspace blocks. Use the result of e for Digital Controller. Select an appropriate time for simulation and run it by clicking on the start button. e) Plot the Y(t) by using t and ytSampled. Compare the results with a and b. f) Repeat c, d, and e for de-gain values are 10,100, and 1000. g) Discuss the effect of the phase-lag compensator for different de-gain values (Hint: Consider both the transient and steady-state responses). Does the increment in the de-gain destabilize this system? Explain your answer by proving the mathematical expressions.
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