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Texas A&M University *

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248

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Electrical Engineering

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Apr 3, 2024

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ECEN 248: Introduction to Digital Design Department of Electrical and Computer Engineering Texas A&M University Laboratory Exercise #4 Simple Arithmetic Logic Unit Lab exercise created and tested by: Cheng-Yen Lee, Kushagra Gupta, Myung Seok Shim, Abbas Fairouz Zhixing Li, Pierce Cantrell and Sunil P. Khatri

2 Laboratory Exercise #4 1 Introduction In this lab, you will design, implement, and test a simple 4-bit Arithmetic Logic Unit (ALU) which will perform elementary computations such as addition, subtraction, and bit-wise AND. To do so, you will learn about Two’s Complement arithmetic and multiplexers. 2 Background 2.1 Two’s Complement Arithmetic In the previous lab, we briefly introduced addition of unsigned numbers but made no mention of subtraction. In order to perform subtraction, we need a way to represent negative numbers in binary. Therefore, we will introduce a binary signed number representation and show how to use it for subtraction. Note that a binary signed number is simply a binary number that can take on either a positive or negative value. Although there are many ways to represent signed numbers in binary, we will only touch on one such representation in this lab assignment, namely Two’s Complement . First of all, how to compute two’s complement? Just invert all the bits and add 1 to it . Assume we have a 4-bit binary number that is 0101 , what is the two’s complement of it? 1. Invert all the bits: 0101 = 1010 2. Add 1 to the result: 1010 + 1 = 1011 3. Check sum: 0101 + 1011 = 10000 = 2 4 Thus the two’s complement of 0101 is 1011 , or we can say two’s complement of 5 is − 5 . Now you may have the question: 1011 should be 11 , how can it be − 5 ? Next, we are going to learn how to read two’s complement negative binary number. The leftmost bit indicates the sign of number: 0 means positive and 1 means negative. Positive numbers remain the same but negative ones do not. Let us go over the 4-bit binary number 1011 . 1. The leftmost 4th bit is 1 , which means it is negative. 2. Take two’s complement again to determine its magnitude: 1011 + 1 = 0101 = 5 decimal So 1011 is − 5 in two’s complement. To verify it, 0101 + 1011 = 10000 , which is 0 . Here, because we are doing 4-bit binary math, we do not care about the leftmost 5th bit, which is also a carry out bit 1 . 2 ECEN 248

Laboratory Exercise #4 3 Last but not least, there is a small trick for you to extend the original binary number to more bits. For positive numbers, fill the missing bits with 0’s and for negative numbers, fill the missing bits with 1s. 0101 and 1011 are extended to 6-bit numbers as below: 1. 0101 4 − bit = 000101 6 − bit 2. 1010 4 − bit = 111010 6 − bit Up till now, we have been able to represent both positive and negative in binary. Therefore, subtraction can be performed by negating the subtrahend and adding it to the minuend. Figure 1 illustrates the addition of two’s complement numbers. Figure 1: Addition of Two’s Complement Numbers The subtraction on the left generates the result correctly but the addition on the right does not! 1000 is − 8 in two’s complement, not 8 . This situation is called overflow because it exceeds the range of two’s complement. In mathematical terms, the decimal value of a two’s complement binary number belongs in [ − 2 n − 1 , 2 n − 1 − 1] , where n is the number of bits. Thus 4-bit two’s complement cannot represent decimal number 8 , which causes the overflow. Because the result is wrong when overflow has occurred, it must be indicated so that the wrong one can be discarded. For two’s complement arithmetic, overflow occurs when both input sign bits are the same but differ from the output’s sign bit. If there is still something unclear, please consult your text book and lecture slides. 2.2 Multiplexers A multiplexer (MUX for short) is a digital circuit which selects an output from more than one input. Figure 2 provides two such examples, where A , B , C , D , Output , and S are all 1-bit wide. Note that { S 1 , S 0 } represents the concatenation of S 1 and S 0 and is a 2-bit bus (i.e. grouping of signals noted by the diagonal line crossed through the arrow and marked with a “2”). The 2:1 MUX shown in Figure 2(a) outputs A if the selection line, S , is logic 0 and outputs B otherwise. Figure 2(b) depicts a 4:1 MUX which selects from four inputs, A , B , C , or D , based on the binary value ECEN 248 3

4 Laboratory Exercise #4 (a) 2:1 MUX (b) 4:1 MUX Figure 2: Multiplexers of { S 1 , S 0 } . For example, when S 1 = 0 and S 0 = 0 (i.e. { S 1 , S 0 } =“00”), the value of input A is passed through to output . Likewise, when S 1 = 0 and S 0 = 1 (i.e { S 1 , S 0 } =“01” ), the value of input B is passed through. The previous examples depicted 1-bit wide multiplexers; however, it is often necessary to multiplex buses of signals. Figure 3 shows how a 2-bit MUX can be constructed from two 1-bit MUXs. The drawing on the left shows the two MUXs superimposed to create the 2-bit wide MUX on the right. Note that the selection signals, S , have been tied together. We can easily create n -bit wide MUXs in this manner. Figure 3: 2-bit Wide 2:1 MUX In this lab, we are using component SN74CT257N as our chip for the MUX. Its pin-out diagram is shown in Figure 4. The only thing needs to be noticed is that ¯ A/B is the select signal S and OE must be connected 4 ECEN 248

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